For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. The necessity to optimize the performance of each device becomes increasingly significant.
Another trend in the semiconductor industry is to consider system-on-a-chip type architectures. Such architectures may incorporate, for example, an analog device on the same substrate as a logic device. However, the optimization of one type of device may hamper the optimization of another type of device, often making difficult the incorporation of both types of devices into a single system. Such a dilemma may occur, for example, when optimizing the threshold voltage for each type of device.